on-chip bus, network-on-chip), and should include both dynamic and static power consumption. It should focus mainly on the energy dissipated by the on-chip interconnect structure (e.g. The goal of this work is to model energy consumption into a simulation framework for multicores. on Computer Design (ICCD), 2008.ġ2.lsi.4 - Abstract models for estimating energy consumption in multicores Marculescu, “Contention-aware Application Mapping for Network-on-Chip Communication Architectures,” Proc. Moraes, “Congestion-aware task mapping in heterogeneous MPSoCs,” System-on-Chip, 2008. Requirements: good background in algorithms, concurrent programmingĭesired: scheduling algorithms ( RTS / CRT) how much processing overhead is due to the mapping heuristic itself?.which sort of information about the multicore system does the mapping heuristic requires, and how much resources one needs to store and transmit such information?. ![]()
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